In an integrated circuit (IC) design, delay values in a static timing analysis are dependent upon a power supply voltage value, e.g., a positive power supply (VDD) minus a reference power supply, or ground, (GND). VDD and GND values may vary both spatially, i.e., across different locations on an IC chip, and/or temporally, i.e., in time. A power supply with such spatial and/or temporal variations of voltage values may be referred to as a transient power supply. In an IC design, specifically, a timing analysis of an IC design, problems of a transient power supply need to be considered and accommodated.
Efforts have been made to accommodate the problem of transient power supply in IC designs. For example, some approaches use a one-for-all (global) supply voltage value (VDD−GND) to calculate delays for each and all elements (or blocks of elements) in an IC chip during a static timing analysis. Alternatively, a pair of global supply values (upper end v. lower end) may be specified, where the upper end is used to calculate early mode delays and the lower end is used to calculate late mode delays. These approaches are disadvantageous in that they do not account for either the temporal or the spatial variations in voltage value.
Some other approaches analyze a power bus (e.g., via a simulation) to determine a power supply voltage value at each location (of elements) in an IC chip. A voltage value based on leakage current or average current demand at a location of an element is then used to calculate a delay for the element. These approaches are disadvantageous because they fail to account for temporal variation in supply voltage. In addition, these approaches do not directly relate a voltage value used in a timing analysis to a power bus analysis, e.g., a power bus simulation.
Hathaway et al. (U.S. patent application Ser. No. 11/095,327, incorporated herein by reference) provide a superposition-based method. According to Hathaway et al., separate power bus analyses are performed to obtain the transient voltage responses resulting from different switching objects or groups of switching objects on the chip. These separate power bus analyses are then used in a static timing analysis to obtain the worst timing behavior that can occur for any combination (or any “allowed” combination) of these switching objects or groups of objects. Hathaway et al. account for both spatial and temporal power supply variations, and provide better coverage of all possible chip activity patterns. Unfortunately, the run time cost for determining the worst case superposition of activities may be quite expensive.
Based on the above, there is a need to analyze static timing of an IC element with a transient power supply in consideration of a static timing slack of the element in the context of a timing path.